Title:
半導体集積回路装置の製造方法
Document Type and Number:
Japanese Patent JP4099412
Kind Code:
B2
Abstract:
The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
Inventors:
Yuji Wada
Kasukabe Susumu
Takehiko Hasebe
Naritsuka Yasunori
Akira Yabushita
Mori Teruki
Akio Hasebe
Yasuhiro Motoyama
Teruji Shoji
Sueyoshi Masakazu
Kasukabe Susumu
Takehiko Hasebe
Naritsuka Yasunori
Akira Yabushita
Mori Teruki
Akio Hasebe
Yasuhiro Motoyama
Teruji Shoji
Sueyoshi Masakazu
Application Number:
JP2003075429A
Publication Date:
June 11, 2008
Filing Date:
March 19, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/66; G01R1/073
Domestic Patent References:
| JP9203749A | ||||
| JP64004042A | ||||
| JP2001091544A | ||||
| JP2000002746A |
Attorney, Agent or Firm:
Yamato Tsutsui