Title:
不揮発性半導体記憶装置及びその製造方法
Document Type and Number:
Japanese Patent JP4104133
Kind Code:
B2
Abstract:
A non-volatile semiconductor memory device comprise a source region 44 and a drain region 46 formed in a semiconductor substrate 30; a gate electrode 36 formed on the semiconductor substrate between the source region and the drain region with a first insulation film 32 formed between the gate electrode and the semiconductor substrate; and a charge accumulation region 42a, 42b of a dielectric material, which is formed on at least either of the side wall of the gate electrode on the side of the source region and the side wall of the gate electrode on the side of the drain region. Accordingly, charges accumulated on the side of the source region 44 and the charges accumulated on the side of the drain region 46 can be easily spatially isolated from each other.
Inventors:
Fukuda Masatoshi
Taro Sugisaki
Toshiro Nakanishi
Nara Yasuo
Taro Sugisaki
Toshiro Nakanishi
Nara Yasuo
Application Number:
JP2003132041A
Publication Date:
June 18, 2008
Filing Date:
May 09, 2003
Export Citation:
Assignee:
Spansion LLC
International Classes:
H01L21/8247; H01L21/28; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP9097849A | ||||
| JP2003332474A | ||||
| JP2000004014A | ||||
| JP63204770A | ||||
| JP61241966A |
Attorney, Agent or Firm:
Shuhei Katayama