Title:
デジタルチューナ用多層基板および多層基板
Document Type and Number:
Japanese Patent JP4106568
Kind Code:
B2
Abstract:
Mounting components such as LSIs, which emit noise to the outside and are subjected to the influence of external noise, on the top-most layer and the bottom-most layer respectively, a co-existing layer of the ground region and the power source region has been employed, where a ground region has been provided respectively to the range corresponding to the position the LSIs on the next layer below the top-most layer and the next layer above the bottom-most layer. Accordingly, the number of layers to be laminated to form the multilayer substrate has been reduced, because it is no longer required, unlike the related art, to provide a ground layer where the ground pattern is formed substantially over the entire surface of layer respectively to the next layer below the top-most layer having mounted a LSI thereon and of the next layer above the bottom-most layer having mounting a LSI thereon.
Inventors:
Yamanaka Yasuhisa
Application Number:
JP2005278792A
Publication Date:
June 25, 2008
Filing Date:
September 26, 2005
Export Citation:
Assignee:
Funai Electric Co., Ltd.
International Classes:
H05K3/46
Domestic Patent References:
| JP2005136235A | ||||
| JP10313178A | ||||
| JP10290055A | ||||
| JP9018156A | ||||
| JP63170988A | ||||
| JP2003133747A |
Attorney, Agent or Firm:
Toshiyuki Yokoi