半導体装置の製造方法

Japanese Patent JP4110390

B2

A depression (22) is formed from a first surface (20) of a semiconductor substrate (10). An insulating layer (28) is provided on the bottom surface and an inner wall surface of the depression (22). A conductive portion (30) is provided inside the insulating layer (28). A second surface (38) of the semiconductor substrate (10) is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate (10) is greater than the etching amount with respect to the insulating layer (28), and the conductive portion (30) is caused to project while covered by the insulating layer (28). At least a portion of the insulating layer (28) formed on the bottom surface of the depression (22) is etched with a second etchant having characteristics such that at least the insulating layer (28) is etched without forming a residue on the conductive portion (30), to expose the conductive portion (30).

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Ikuya Miyazawa

JP2003007277A

July 02, 2008

January 15, 2003

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Seiko Epson Corporation

H01L23/12; H01L23/52; H01L21/301; H01L21/3205; H01L21/768; H01L23/48; H01L23/485; H01L25/065; H01L25/07; H01L25/18; H01L21/306; H01L21/78; H01L23/31

JP2001053218A
JP60007148A
JP11195641A
JP10268526A
JP11345933A
JP2000311981A
JP2002025948A
JP60007149A
JP2001326325A
JP2000510288A

Yukio Fuse
Mitsue Obuchi

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