Title:
サンプルホールド回路
Document Type and Number:
Japanese Patent JP4117976
Kind Code:
B2
Abstract:
In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).
Inventors:
Shigenobu Takeshi
Masao Ito
Kumamoto Toshio
Masao Ito
Kumamoto Toshio
Application Number:
JP16392899A
Publication Date:
July 16, 2008
Filing Date:
June 10, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H03M1/34; G11C27/02; H03K5/08
Domestic Patent References:
| JP10500820A | ||||
| JP1285096A | ||||
| JP57060593A | ||||
| JP11127080A | ||||
| JP4061521A | ||||
| JP58071724A | ||||
| JP6140212A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa