Title:
電子装置
Document Type and Number:
Japanese Patent JP4121543
Kind Code:
B1
Abstract:
There are provided the steps of forming a bump 104 on an electrode pad 103 provided on a semiconductor chip 101, forming a low-modulus insulating layer 120 on the semiconductor chip 101 and laminating, on the low-modulus insulating layer 120, a high-modulus insulating layer 121 having a higher elastic modulus than an elastic modulus of the low-modulus insulating layer 120, thereby forming a laminated insulating layer 105, exposing a part of the bump 104 from an upper surface of the laminated insulating layer 105, and forming a conductive pattern 106 connected to the bump 104.
Inventors:
Koji Yamano
Nao Arai
Nao Arai
Application Number:
JP2007160614A
Publication Date:
July 23, 2008
Filing Date:
June 18, 2007
Export Citation:
Assignee:
Shinko Electric Industry Co., Ltd.
International Classes:
H01L23/12; H01L21/60
Domestic Patent References:
| JP9064049A | ||||
| JP2004363250A | ||||
| JP2001118876A | ||||
| JP2005158929A | ||||
| JP2004006486A |
Attorney, Agent or Firm:
Tadahiko Ito
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