Title:
記憶回路及びメモリセンス増幅回路
Document Type and Number:
Japanese Patent JP4138878
Kind Code:
B2
Abstract:
A differential sense amplifier includes positive feedback cross coupling to control operation in one mode as a differential sense amplifier and in another mode as a latch to control a data-latching load. Circuit nodes are precharged and equalized in response to applied enable signal.
Inventors:
Mu, Albert
Application Number:
JP53020297A
Publication Date:
August 27, 2008
Filing Date:
February 12, 1997
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/419; G11C7/06; G11C11/409; G11C11/4091
Domestic Patent References:
| JP7050095A | ||||
| JP7141874A | ||||
| JP8007575A |
Attorney, Agent or Firm:
Takashi Ishida
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama