Title:
増分デルタ・アナログ/ディジタル変換器
Document Type and Number:
Japanese Patent JP4139332
Kind Code:
B2
Abstract:
A method of, and a converter for, converting an analogue input signal (X) to a digital output signal (Y) by incremental-delta conversion in which, at clock intervals, a non-uniform quantizer (7) produces digital quantizer signals, a digital-to-analogue converter (5) produces analogue quantizer signals that are a function of the digital quantizer signals, analogue difference signals (Q) are applied over a feedback loop to the quantizer (7) that are a function of the difference between the input signal (X) and the integral of the analogue quantizer signals since a reset signal, and the digital output signal (Y) is produced as a function of the sum of the digital quantizer signals since the reset signal. The digital quantizer signals have a first magnitude (q) if the magnitude of the analogue difference signals (Q) is less than a threshold magnitude (Vt) and a second magnitude (r), substantially greater than the first magnitude (q), if the magnitude (Q) of the analogue difference signals is greater than the threshold magnitude (Vt), the threshold magnitude (Vt) being substantially less than the magnitude (Vr) of the analogue quantizer signals corresponding to the second magnitude (r). The magnitude of the change in the analogue difference signals (Q) between two successive clock cycles is substantially less than the magnitude of the corresponding analogue quantizer signals (Vq, Vr), so that the gain (g) of the feedback loop from the digital-to-analogue converter (5) to the quantizer (7) is substantially less than one.
Inventors:
Oriaei, Omid
Leme, Berengère
Leme, Berengère
Application Number:
JP2003541146A
Publication Date:
August 27, 2008
Filing Date:
October 23, 2002
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H03M1/82; H03M3/02
Domestic Patent References:
| JP62051826A |
Foreign References:
| US5550544 |
Other References:
A.Yufera et al.,S2I First-order Incremental A/D Converter,IEE Proceedings - Circuits Devices Systems,IEE,1998年 4月,Vol.145, No.2,pp.78-84
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
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