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Title:
半導体樹脂封止用金型
Document Type and Number:
Japanese Patent JP4153862
Kind Code:
B2
Abstract:

To provide an expensive semiconductor resin sealing die which can eliminate the need of a flash removal step and solve problems of scratches in the contact of a substrate caused by resin flashes and a connection failure caused by the deposition of the resin flashes, and can prevent wire damage caused by the warpage of the substrate in a resin filling direction by a simple structure and high versatility, by removing resin flashes resulting from a gap between the die and the substrate.

Approaching pins 1 each having a tilted surface in its lower end are provided to be projected at positions which are located at edges of opposing surfaces of an upper cavity block 23 adjacent to cull blocks 25, and correspond to positioning holes 71a of a substrate 70. When the substrate 70 is clamped by the upper and lower cavity blocks 23, 53, the tilted surface provided in the lower end 1a of the approaching pin 1 is pushed against the opening edge of the positioning hole 71a of the substrate 70 so that the substrate 70 is slidably moved while being pushed. Consequently, the side end face 72 of the substrate 70 is pushed against the inner side surface of the lower cavity block 53.

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Horiike Makoto
Masuda cultivation
Taiji Mitani
Application Number:
JP2003364656A
Publication Date:
September 24, 2008
Filing Date:
October 24, 2003
Export Citation:
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Assignee:
Daiichi Seiko Co., Ltd.
International Classes:
B29C33/12; H01L21/56; B29K105/22; B29L9/00
Domestic Patent References:
JP2001170961A
JP2001179782A
JP2002154118A
JP2001251100A
Attorney, Agent or Firm:
Hiroshi Yamazaki
Atsushi Maeda
Takanobu Nakajima