Title:
集積回路においてトレンチアイソレーション構造を形成する方法
Document Type and Number:
Japanese Patent JP4168073
Kind Code:
B2
Abstract:
The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently oxidized to form a first dielectric layer (30). The first dielectric layer (30) is then etched and a second dielectric layer (34) is subsequently formed over the etched dielectric layer (32). A portion of the second dielectric layer (34) is then removed using chemical-mechanical polishing to form a void-free trench plug (36) within the trench (22). In addition, reliability is also improved by minimizing subsequent etching of trench plug (36) after it has been formed.
Inventors:
Asanga H. Perera
Application Number:
JP2007001007A
Publication Date:
October 22, 2008
Filing Date:
January 09, 2007
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L21/76; H01L21/762
Domestic Patent References:
| JP60043843A |
Attorney, Agent or Firm:
Yoshiaki Ikeuchi