Title:
ダイナミックバイアス法を採用した線形C級増幅器
Document Type and Number:
Japanese Patent JP4168327
Kind Code:
B2
Abstract:
A power amplifier circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifying transistor to obtain a conduction angle of less than about 180°. The dc bias circuit includes a dynamic biasing circuit for decreasing the dc bias signal provided to the amplifying transistor as the input signal to the power amplifier circuit increases. This configuration permits the amplifier circuit to operate as a linearized Class C amplifier, having a substantially linear input-output relationship similar to that of a Class B amplifier, but with increased operating efficiency.
Inventors:
Tildad, Thorati
Application Number:
JP2002552179A
Publication Date:
October 22, 2008
Filing Date:
December 05, 2001
Export Citation:
Assignee:
NXP B.V.
International Classes:
H03F1/32; H03F3/21; H03F1/02; H03F3/193; H03F3/20
Domestic Patent References:
| JP56039717U | ||||
| JP53056952A | ||||
| JP57021107A | ||||
| JP10303655A | ||||
| JP3065715A | ||||
| JP2000165146A |
Foreign References:
| WO2002003545A1 |
Attorney, Agent or Firm:
Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi
Hidetoshi Tachibana
Takeshi Sekine
Takahashi