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Title:
半導体装置
Document Type and Number:
Japanese Patent JP4176961
Kind Code:
B2
Abstract:
A semiconductor device is disclosed along with a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads as formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for external connection as electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relax layer being adhered thereto, wherein more than one third of the stress relax layer from a surface thereof is cut away for removal and wherein the stress relax layer is subdivided into a plurality of regions. In accordance with the present invention, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.

Inventors:
Akira Nagai
Ueno Takumi
Haruo Akahoshi
Eguchi State
Masahiko Ogino
Toshiya Sato
Asao Nishimura
Ichiro Anjo
Application Number:
JP2000553994A
Publication Date:
November 05, 2008
Filing Date:
June 12, 1998
Export Citation:
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Assignee:
Renesas Technology Corp.
International Classes:
H01L21/60; H01L21/56; H01L23/12; H01L23/485
Domestic Patent References:
JP11340369A
Foreign References:
WO1998032170A1
WO1998040915A1
Attorney, Agent or Firm:
Yukihiko Takada