Title:
記憶装置および画像データ処理装置
Document Type and Number:
Japanese Patent JP4182575
Kind Code:
B2
Abstract:
A storage device and an image data processing apparatus is capable of simplifying input control of an FIFO circuit. It comprises a DRAM capable of storing image data in a plurality of read indication signals giving different data lengths of valid pixel data to be read by one read operation. A FIFO circuit receives as input the valid pixel data read from the DRAM and storing the same. An address generation unit generates a read request for a number of times in accordance with the read indication signal when a predetermined amount of an empty region is generated in the memory region of the FIFO circuit in order that all of the valid pixel data output from the DRAM to the FIFO circuit by the read request be written in the empty region.
Inventors:
Toshiaki Shino
Application Number:
JP31813398A
Publication Date:
November 19, 2008
Filing Date:
November 09, 1998
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06F12/00; G06F3/06; G06F5/12; G06T11/20
Domestic Patent References:
| JP3223973A | ||||
| JP61283952A |
Attorney, Agent or Firm:
Takahisa Sato