再構成可能ハードウエアの模擬方法及び模擬システム - Nippon Telegraph and Telephone Corporation

Title:

再構成可能ハードウエアの模擬方法及び模擬システム

Document Type and Number:

Japanese Patent JP4187102

Kind Code:

B2

Abstract:

To reduce the usage of a memory in executing simulation on dynamically reconfigurable hardware.

When an operation to write a logic circuit in dynamically reconfigurable hardware is simulated, a memory area in which the executing situation of the logic circuit is stored is assigned to an execution time assignment memory 200 by every reconfiguration unit of the logic circuit. As regards the memory area in which the configuration data of the logic circuit are stored, the memory area of the execution time assignment memory 200 is shared by using a reference table 300 when an identifier 3 is applied to the configuration data, and the memory area of the execution time assignment memory 200 is shared by using a hash table 400 when any identifier is not applied to the configuration data, and the simulation is executed.

Inventors:

Ryusuke Konishi
Hideyuki Ito
Hiroshi Nakata

Application Number:

JP2003284704A

Publication Date:

November 26, 2008

Filing Date:

August 01, 2003

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Assignee:

Nippon Telegraph and Telephone Corporation

International Classes:

G01R31/28; G06F17/50

Domestic Patent References:

JP8287113A

Other References:

Lysaght, P. et al.,A simulation tool for dynamically reconfigurable field programmablegate arrays,IEEE Transactions on Very Large Scale Integration (VLSI) Systems,IEEE,1996年 9月,Vol.4, No.3,pp.381~390
永見康一,外2名,プラスティック・セルアーキテクチャの設計を支援するシミュレーション方式,情報処理学会シンポジウムシリーズ,社団法人情報処理学会,1998年 7月16日,第98巻,第9号(DAシンポジウム’98),pp.149~154
中根良樹,外5名,自律再構成可能アーキテクチャPCAにおける実行時資源管理の方法,情報処理学会シンポジウムシリーズ,社団法人情報処理学会,2001年 7月23日,第2001巻,第8号(DAシンポジウム2001),pp.67~72

Attorney, Agent or Firm:

Tsuneaki Nagao

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