Title:
プローブカード
Document Type and Number:
Japanese Patent JP4187718
Kind Code:
B2
Abstract:
A probe card for a wafer level test of electrical characteristics of a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer. The card has a thin film with bumps on which a plurality of bumps to be respectively brought into contact with all of inspection electrodes of the semiconductor integrated circuit devices are formed, and which is held on a rigid ceramic ring. An alignment mark constituted by a bump formed simultaneously with the bumps for contact is added to the thin film with bumps. The desired position of the alignment mark relative to the bumps for contact is maintained. Therefore, a change in position accuracy of the bumps for contact can be easily measured by an image processor with reference to the alignment mark. An optimum position for contact between the wafer to be inspected and the inspection electrodes on the wafer can be computed from the measurement result.
Inventors:
Kenji Yamada
Yoshiro Nakata
Yoshiro Nakata
Application Number:
JP2004366936A
Publication Date:
November 26, 2008
Filing Date:
December 20, 2004
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/66
Domestic Patent References:
| JP11154694A |
Attorney, Agent or Firm:
Yoshihiro Morimoto
Toshiji Sasahara
Yohei Harada
Toshiji Sasahara
Yohei Harada
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