Title:
電圧制御発振器の遅延セル
Document Type and Number:
Japanese Patent JP4199972
Kind Code:
B2
Abstract:
A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator ("VCO") includes a plurality of such delay cells connected in a closed loop series. Phase locked loop ("PLL") circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.
Inventors:
Schepan William Andrasick
Rakesh H Patel
Chung H Lee
Rakesh H Patel
Chung H Lee
Application Number:
JP2002272354A
Publication Date:
December 24, 2008
Filing Date:
September 18, 2002
Export Citation:
Assignee:
Altera Corporation
International Classes:
H03K5/13; H03H11/26; H03K3/03; H03K3/354; H03L7/099; H03L7/10
Domestic Patent References:
| JP6326573A | ||||
| JP10041397A | ||||
| JP4293313A |
Foreign References:
| US6072372 |
Attorney, Agent or Firm:
Haruo Hamada