Title:
マルチプレシジョン整数演算用の装置
Document Type and Number:
Japanese Patent JP4201980
Kind Code:
B2
Abstract:
A system and method for performing multiplication and modular reduction of large integers. The system includes at least one large integer unit (21), each large integer unit having a multiplier (22), an adder (23), and a register (24). First and second multiplier inputs are applied to the multiplier, and first and second adder inputs are applied to the adder. One output of the multiplier is also applied to the adder. A plurality of large integer units may be connected into a large integer unit array (39) that includes a complementing gate (35) and a latching register (34). A second output of the multiplier is applied to the first adder input of a next large integer unit, with processing speed increasing as additional large integer units are added to the array.
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| JPS63223825 | DATA TYPE CONVERTING CIRCUIT |
Inventors:
Sabin Michael Jay.
Haysin Mark W.
Haysin Mark W.
Application Number:
JP2000522511A
Publication Date:
December 24, 2008
Filing Date:
November 04, 1998
Export Citation:
Assignee:
ATMEL CORPORATION
International Classes:
G06F7/00; G09C1/00; G06F7/52; G06F7/544; G06F7/72
Domestic Patent References:
| JP2000503146A | ||||
| JP6012229A | ||||
| JP62097060A |
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Kazuo Abe