ディジタル信号をプリエンファシス伝送路経由で送信するための出力バッファ回路

Japanese Patent JP4215896

B2

The present invention relates to an output buffer circuit for transmitting digital signals over a transmission line with pre-emphase. It comprises an output stage and a control circuit. The output stage includes a first impedance circuit connected between an upper power supply potential and an output node. It furthermore includes a second impedance circuit connected between the output node and a power supply node at a lower supply potential. Both impedance circuits receive impedance control signals from the control circuit such that an impedance ratio between the first impedance and the second impedance takes one of at least three different predetermined values in accordance with the present state and the history of a digital data input signal, and such that the sum of the conductance provided by the first impedance circuit and the conductance provided by the second impedance circuit is independent from the generated impedance ratios. Preferably, both impedance circuits consist of a plurality of transistors connected in parallel. For each transistor in the first impedance circuit there exists a corresponding transistor in the second impedance circuit. Pairs of corresponding transistors are designed to have the same ON-impedance. The control circuit controls the first and the second impedance circuit such that in each pair one transistor is in the ON state and the other transistor is in the OFF state at any time.

Mats Hedberg

JP15853499A

January 28, 2009

June 04, 1999

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Telefon Akti Bora Get Elm Ericson (Pubble)

H03K19/0175; H04B3/04; H04L25/02

JP8286794A
JP8032435A
JP7142985A
JP11345054A
JP11008545A

Hideto Asamura
Hajime Asamura
Masaaki Utsunomiya
Hayashi Zouzo

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