Title:
ルテニウム及びタングステンを含有する層の形成方法、及びこれら層を含む集積回路構造体
Document Type and Number:
Japanese Patent JP4216585
Kind Code:
B2
Abstract:
Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
Inventors:
Vishinu Kei Agerwal
Gallo Delderian
Hartei S Sandoo
Wei Min Emry
Mark Bizokei
Tsum Basqueri
Sam Yang
Gallo Delderian
Hartei S Sandoo
Wei Min Emry
Mark Bizokei
Tsum Basqueri
Sam Yang
Application Number:
JP2002502821A
Publication Date:
January 28, 2009
Filing Date:
June 07, 2001
Export Citation:
Assignee:
MICRON TECHNOLOGY, INC.
International Classes:
H01L21/822; H01L27/04; H01L21/02; H01L21/8242; H01L27/108
Domestic Patent References:
| JP9017972A | ||||
| JP11121711A | ||||
| JP11274431A | ||||
| JP10163131A |
Foreign References:
| WO1999066558A1 |
Attorney, Agent or Firm:
Kosaku Sugimura