Title:
半導体パッケージ
Document Type and Number:
Japanese Patent JP4216825
Kind Code:
B2
Abstract:
Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.
Inventors:
Satoshi Nakamura
Taku Suga
Mitsuaki Katagiri
Yukitoshi Hirose
Taku Suga
Mitsuaki Katagiri
Yukitoshi Hirose
Application Number:
JP2005081261A
Publication Date:
January 28, 2009
Filing Date:
March 22, 2005
Export Citation:
Assignee:
株式会社日立製作所
エルピーダメモリ株式会社
エルピーダメモリ株式会社
International Classes:
G01R31/28; G11C29/02; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP2000332192A | ||||
| JP2004158098A | ||||
| JP2003158239A |
Attorney, Agent or Firm:
Polaire Patent Business Corporation
Katsuo Ogawa
Kyosuke Tanaka
Katsuo Ogawa
Kyosuke Tanaka
Previous Patent: ３次元モデル生成装置、３次元モデル生成方法および３次元モデル生成プ...
Next Patent: MANUFACTURE OF POLY (ARYLENE SULFIDE SULFONE)
Next Patent: MANUFACTURE OF POLY (ARYLENE SULFIDE SULFONE)