To suppress voltage drop and signal delays by attaining low resistance of wiring in a display panel.

This display panel is equipped with a transistor array substrate 50 in which transistors 21-23 and a capacitor 24 are provided per single dot subpixel P. Scanning lines X, supply lines Z in the horizontal direction and signal lines Y in the perpendicular direction are laid on the transistor array substrate 50. Common wiring 62 and supply wiring 61 are projected on the surface of the transistor array substrate 50. A subpixel substrate 20a is arranged between the common wiring 62 and the supply wiring 61, and an organic EL layer 20b is stacked on the subpixel electrode 20a. The common wiring 62 is conducted with an opposite electrode 20c. Supply thick-film wiring 82 and common thick film wiring 83, capable of adjusting thick film provided on a sealing substrate 80 are conducted, independently of the supply wiring 61 and the common wiring 62.

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