Title:
ATM装置及びATMパケット構成方法
Document Type and Number:
Japanese Patent JP4223610
Kind Code:
B2
Abstract:
An ATM circuit for use in re-assembly of ATM cells containing ATM payloads comprising an input unit for receiving interleaved ATM cells derived from ATM packets relating to respective virtual channels and a checker for checking the ATM cells of an ATM packet of a selected virtual channel with respect to ATM packet trailer information contained in the ATM cells of the ATM packet, the ATM circuit being configured to output the ATM cell payloads in the original interleaved state, a main processor being configured to receive the ATM payloads output by the ATM circuit and to deinterleave the ATM cell payloads by storing the ATM cell payloads in a memory, the checker producing check data representing the results of the checking and the ATM circuit being configured to output the check data together with corresponding ATM cell payloads.
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Inventors:
Arthur Simon Waller
Application Number:
JP36849998A
Publication Date:
February 12, 2009
Filing Date:
December 09, 1998
Export Citation:
Assignee:
Sony United Kingdom Limited
International Classes:
H04L12/56; H04Q3/00; H04Q11/04
Domestic Patent References:
| JP6326726A |
Foreign References:
| US5642347 |
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga