Title:
レートデマッチング処理装置
Document Type and Number:
Japanese Patent JP4224688
Kind Code:
B2
Abstract:
(3n+1)th (n = 0, 1, 2, ···, M/3-1) input data is stored in a first memory 102, (3n+2)th (n = 0, 1, 2, ···, M/3-1) input data is stored in a second memory 103, and (3n+3)th (n = 0, 1, 2, ···, M/3-1) input data is stored in a third memory 104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108, a first parity bit queue 109, and a second parity bit queue 110, respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.
Inventors:
Daiji Ishii
Application Number:
JP2003173297A
Publication Date:
February 18, 2009
Filing Date:
June 18, 2003
Export Citation:
Assignee:
NEC
International Classes:
H04L29/08; H03M13/27; H04L1/00; H04L1/08
Domestic Patent References:
| JP2002199048A | ||||
| JP6343083A | ||||
| JP2002208863A | ||||
| JP2002271209A |
Attorney, Agent or Firm:
Akio Miyazaki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki