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Title:
半導体装置
Document Type and Number:
Japanese Patent JP4225794
Kind Code:
B2
Abstract:

To solve the problem of a semiconductor device, especially of a QFN type package, wherein the packaging area is small because only the exposed surface of a lead is used and since the packaging area is increased by exposing an island, a lead is not packaged due to difference of the exposed areas.

In the semiconductor device, a lead 23, a part 27 of a square island and a part 28 of a round island are exposed from the rear surface 26 of a resin package 22. More specifically, parts 27 and 28 of the island are exposed from the rear surface of the resin package 22 in order to enhance mounting strength and their exposed areas are balanced thus preventing solder from being shifted at the lower parts of the lead 23 and the parts 27 and 28 of the island. Consequently, a desired lead and a conductive pattern are packaged surely in the semiconductor device.

COPYRIGHT: (C)2004,JPO&NCIPI


Inventors:
Toshiyuki Take
Tetsuya Fukushima
Application Number:
JP2003011650A
Publication Date:
February 18, 2009
Filing Date:
January 20, 2003
Export Citation:
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Assignee:
Sanyo Electric Co., Ltd.
Kanto Sanyo Semiconductors Co., Ltd.
International Classes:
H01L23/12; H01L23/50
Domestic Patent References:
JP2001358276A
JP10247715A
JP11233683A
JP63042132A
Attorney, Agent or Firm:
Takashi Okada
Katsuhiko Sudo