Title:
入力バッファ回路、及び半導体装置の動作試験方法
Document Type and Number:
Japanese Patent JP4226710
Kind Code:
B2
Abstract:
An input buffer circuit includes a differential amplifier that receives a input signal and its complement and generates an amplified signal corresponding to the voltage difference between the input signal and its complement. A transfer circuit receives the input signal and generates a transfer signal having the same logical value as the input signal. A control circuit connected to the differential amplifier and the transfer circuit selects one of the amplified signal and the transfer signal for output by enabling either the differential circuit or the transfer circuit.
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Inventors:
Masahito Isoda
Application Number:
JP1615999A
Publication Date:
February 18, 2009
Filing Date:
January 25, 1999
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G01R31/28; H03F1/00; H03F3/72; H03F3/343; H03F3/45; H03K17/693; H03K19/00; H03K19/0175; H03K19/0185; H03K19/094
Domestic Patent References:
| JP10209844A | ||||
| JP3196279A | ||||
| JP10209772A | ||||
| JP4114504A | ||||
| JP8018354A |
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda
Makoto Onda
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