Title:
データプロセッサ
Document Type and Number:
Japanese Patent JP4230504
Kind Code:
B2
Abstract:
The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation. The data processor is arranged as a data processor having typical functions as an integrated whole of processors (CPU1 and CPU2) which execute simple instruction flows. When executing the instruction having a direction for write to a reference register of other instruction flow, the processor confirms whether a write register is invalid. The processor waits for the register to be made invalid, if the register is not invalid, and performs write if the register is invalid. After having executed the instruction having a direction for reference register invalidation, the processor invalidates the register to which a reference has been made. When the reference register is invalid, execution of the referring instruction is suspended until it is made valid.
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Inventors:
Fumio Arakawa
Application Number:
JP2006323537A
Publication Date:
February 25, 2009
Filing Date:
November 30, 2006
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F9/38
Domestic Patent References:
| JP7311750A |
Attorney, Agent or Firm:
Shizuyo Tamamura