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Title:
シェーディング補正回路
Document Type and Number:
Japanese Patent JP4245140
Kind Code:
B2
Abstract:

To provide a shading correction circuit which suppresses storage capacity for memorizing correction values, and can realize high precision shading correction.

In the shading correction circuit 1, either one address of main scanning direction or sub-scanning direction is created for respective image data in a image region by an address creation means 2. In an address conversion means 3, an address of an address creation means 2 is converted in a specified conversion mode corresponding to an inputted mode selection signal MA. A storage means 4 stores correction coefficients corresponding to addresses of the address conversion means 3, and an operation means 5 makes operation for shading correction using correction coefficients read from the storage means 4 based on the address of the address conversion means 3, and image data inputted from an imaging element.

COPYRIGHT: (C)2005,JPO&NCIPI


Inventors:
Tomohiro Fukuoka
Application Number:
JP2003114736A
Publication Date:
March 25, 2009
Filing Date:
April 18, 2003
Export Citation:
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Assignee:
Fujitsu Microelectronics Limited
International Classes:
G06T1/00; G06T1/60; H04N1/19; H04N1/401; H04N5/16; H04N5/243; H04N5/335; H04N5/361; H04N5/372; H04N5/374
Domestic Patent References:
JP2000069359A
JP2001016509A
JP9130603A
JP5176216A
JP2002131623A
JP2003018472A
JP9307789A
JP6197266A
Attorney, Agent or Firm:
Hironobu Onda
Makoto Onda



 
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