Title:
半導体メモリ
Document Type and Number:
Japanese Patent JP4246977
Kind Code:
B2
Abstract:
A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder successively selects column selecting lines in synchronization with the column pulses. A plurality of bits of data read from memory cells in response to a single read command RD is successively transmitted to a common data bus line through column switches. This can reduce the number of data bus lines to a minimum, preventing an increase in chip size. Since a single data bus line can transmit a plurality of bits of data, it is possible to minimize the size of the memory region to be activated in response to a read command. This consequently allows a reduction in power consumption.
Inventors:
Junichi Sasaki
Shinozaki saki Naoji
Shinozaki saki Naoji
Application Number:
JP2002251850A
Publication Date:
April 02, 2009
Filing Date:
August 29, 2002
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/407; G11C11/4076; G11C7/00; G11C7/10; G11C7/22; G11C11/401
Domestic Patent References:
| JP20016359A | ||||
| JP11288590A | ||||
| JP2001344973A |
Attorney, Agent or Firm:
Furuya Fumio
Toshihide Mori
Toshihide Mori