Title:
集積回路及びその回路設定生成方法
Document Type and Number:
Japanese Patent JP4258671
Kind Code:
B2
Abstract:
To easily obtain a plurality of circuit designs by only carrying out circuit setting once with a mapping tool.
In this integrated circuit, at least some of connecting wires between an array of basic tiles for constructing a reconstructable integrated circuit are connected in an n (n denotes an integer ≥1) dimensional torus shape. In the circuit setting formation method for this integrated circuit, a plurality of different circuit settings having the same function achieved on the reconstructable integrated circuit, but having performance obeying different probability variables are formed by moving one circuit setting in the torus-shaped connection direction in the basic tile array.
COPYRIGHT: (C)2008,JPO&INPIT
Inventors:
Youhei Matsumoto
Kohei Hohei
Kohei Hohei
Application Number:
JP2006204983A
Publication Date:
April 30, 2009
Filing Date:
July 27, 2006
Export Citation:
Assignee:
National Institute of Advanced Industrial Science and Technology
International Classes:
H01L21/82; H03K19/173
Domestic Patent References:
JP4369120A | ||||
JP63070345A | ||||
JP11330248A |
Foreign References:
WO2005109646A1 |