Title:
半導体素子の低誘電率絶縁膜の蒸着方法
Document Type and Number:
Japanese Patent JP4262676
Kind Code:
B2
Abstract:
The present invention relates to a process for vapor depositing alow dielectric insulating film, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device.
Inventors:
Yang, Sun-Hong
Cernie a., Glenn
Chun, Kyuha
Fun, Byun-Kun
Hong, one-chic
Cernie a., Glenn
Chun, Kyuha
Fun, Byun-Kun
Hong, one-chic
Application Number:
JP2004506072A
Publication Date:
May 13, 2009
Filing Date:
July 16, 2002
Export Citation:
Assignee:
Samsung Electronics Company Limited
DOW CORNING CORPORATION
DOW CORNING CORPORATION
International Classes:
G02F1/1333; H01L21/316; C23C16/40; G02F1/1368; H01L21/205; H01L21/768; H01L23/522; G02F1/1362; H01L23/532
Domestic Patent References:
| JP2005526387A | ||||
| JP2001332550A | ||||
| JP9148322A | ||||
| JP3036269A | ||||
| JP4191374A | ||||
| JP2001326222A | ||||
| JP10242143A | ||||
| JP11054504A | ||||
| JP10275804A | ||||
| JP2001051303A | ||||
| JP2002026331A | ||||
| JP2001284453A | ||||
| JP2001242630A |
Foreign References:
| WO2003097897A1 |
Attorney, Agent or Firm:
Yukio Ono
Tomoko Inazumi
Tomoko Inazumi