Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP4263818
Kind Code:
B2
Abstract:
The present invention provides an input circuit having small current consumption in a clock synchronization type semiconductor integrated circuit. The input circuit is activated by an activation signal to receive an input signal and an activation signal generating circuit generates the activation signal. The activation signal generating circuit activates intermittently the activation signal for a time shorter than a period of a clock signal and including a setup time and a hold time of the input signal in order to activate the input circuit. The input circuit is activated only for the limited time of one period of the clock signal and therefore current consumption can be reduced.
Inventors:
Hiroyuki Tomita
Shinozaki saki Naoji
Shinozaki saki Naoji
Application Number:
JP26632499A
Publication Date:
May 13, 2009
Filing Date:
September 20, 1999
Export Citation:
Assignee:
Fujitsu Microelectronics Limited
International Classes:
G11C11/409; G11C11/4093; G11C8/06; G11C11/401; G11C11/407; G11C11/4076; G11C11/408; H03K3/012; H03K3/356; H03K5/13; H03K5/1534; H03K17/00; H03K19/0175
Domestic Patent References:
| JP7141870A | ||||
| JP2141993A | ||||
| JP5181560A | ||||
| JP10079663A | ||||
| JP7045075A | ||||
| JP9198875A |
Attorney, Agent or Firm:
Takayoshi Kokubun