Title:
ドライエッチングを用いた半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4270632
Kind Code:
B2
Abstract:
There is provided a method of forming an interlayer insulating film having a dual-damascene structure, a contact hole and a deep trench mask using an organic silicon film. The shape of polysilane or the like is processed so that polysilane is used as an interlayer insulating film having a dual-damascene structure to control the shape and depth and prevent borderless etching which must be solved when a trench is formed. Polysilane and an insulating film are formed into a laminated structure so as to be integrated with each other after a dry etching step has been completed to easily form a contact hole having a high aspect ratio. The surface of polysilane is selectively formed into an insulating film so as to be used as a mask for use in a dry etching step. Polysilane for use as an anti-reflective film or an etching mask is changed to an oxide film or a nitride film so that films are easily removed. Hence it follows that a device region and a device isolation region of a densely integrated circuit can be smoothed, a self-aligned contact hole and metallization trench can be formed with a satisfactory manufacturing yield and the pattern of a gate electrode can be formed.
Inventors:
Wataru Seta
Makoto Sekine
Naofumi Nakamura
Makoto Sekine
Naofumi Nakamura
Application Number:
JP6629399A
Publication Date:
June 03, 2009
Filing Date:
March 12, 1999
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/302; H01L21/768; H01L21/28; H01L21/3065; H01L21/311; H01L21/312; H01L21/336; H01L21/76; H01L29/78
Domestic Patent References:
| JP8204001A | ||||
| JP5055387A | ||||
| JP2106948A | ||||
| JP10209134A | ||||
| JP2000003958A |
Attorney, Agent or Firm:
Takehiko Suzue
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Shoji Kawai