Title:
ディジタル処理コンポーネントの給電レベルを調節するシステム及びこれを動作させる方法
Document Type and Number:
Japanese Patent JP4280640
Kind Code:
B2
Abstract:
There is disclosed control circuitry for adjusting a power supply level, VDD, of a digital processing component having varying operating frequencies. The control circuitry comprises N delay cells and power supply adjustment circuitry. The N delay cells are coupled in series, each of which has a delay D determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells. The power supply adjustment circuitry capable of adjusting VDD and is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD in response thereto.
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Inventors:
Maximovic, Dragan
Dal, Sandeep
Dal, Sandeep
Application Number:
JP2003562768A
Publication Date:
June 17, 2009
Filing Date:
January 17, 2003
Export Citation:
Assignee:
NATIONAL SEMICONDUCTOR CORPORATION
International Classes:
H03K19/00; G06F1/26; G06F1/32
Domestic Patent References:
| JP6076571A | ||||
| JP6104720A | ||||
| JP6261450A | ||||
| JP2001184863A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo
Hajime Asamura
Kuniaki Shimizu
Hayashi Zouzo