Title:
酸化物およびポリシリコン・スペーサによる高密度集積回路の製造方法
Document Type and Number:
Japanese Patent JP4302785
Kind Code:
B2
Abstract:
The preset invention provides a method of manufacturing miniature interconnects and capacitors for semiconductor memory devices. The method uses a configuration of two sets of spacers to form self aligned source/bit line contacts and capacitor storage electrodes. First spacers are formed on the sidewalls of an interlevel dielectric layer. The first spacers define the source/bit line contacts holes. Later, the second spacers are formed the sidewalls of the bit lines. The second spacers define the capacitor storage electrodes. The self-aligning process, which uses the two set of spacers, allows a wide processing overlay window for contact etching to form the contact holes and permits small contact holes with high aspect ratios. The method reduces the masking steps by defining both the source and drain contacts in the same masking step.
Inventors:
Zheng Xuyuan
Ei Rui
Ei Rui
Application Number:
JP14555197A
Publication Date:
July 29, 2009
Filing Date:
June 03, 1997
Export Citation:
Assignee:
World-leading Sekisui Electric Circuit Co., Ltd.
International Classes:
H01L21/8242; H01L27/108
Attorney, Agent or Firm:
Makoto Hagiwara