Title:
半導体集積回路装置の製造方法
Document Type and Number:
Japanese Patent JP4322330
Kind Code:
B2
Abstract:
A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or "synthetic" pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.
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Inventors:
Kawakita Keizo
Kazuhiko Kajitani
Seiji Narui
Nakai Kiyoshi
Fumiyoshi Sato
Kazushige Suzuki
Hideaki Tsugane
Kazuhiko Kajitani
Seiji Narui
Nakai Kiyoshi
Fumiyoshi Sato
Kazushige Suzuki
Hideaki Tsugane
Application Number:
JP25160998A
Publication Date:
August 26, 2009
Filing Date:
September 04, 1998
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
H01L21/82; H01L21/8242; H01L23/525; H01L27/00; H01L27/10; H01L21/02; H01L27/108
Domestic Patent References:
| JP6349926A | ||||
| JP3129855A | ||||
| JP2307206A |
Attorney, Agent or Firm:
Akio Miyazaki
Ishibashi Masayuki
Masaaki Ogata
Ishibashi Masayuki
Masaaki Ogata