Title:
半導体接合素子
Document Type and Number:
Japanese Patent JP4326968
Kind Code:
B2
Abstract:
A pin junction element (10) includes a ferromagnetic p-type semiconductor layer (11) and a n-type semiconductor layer (12) which are connected via an insulating layer (13), and which shows a tunneling magnetic resistance according to the magnetization of the ferromagnetic p-type semiconductor layer (11) and the magnetization of the ferromagnetic n-type semiconductor layer (12). In this pin junction element (10), an empty layer is formed with an applied bias, thereby generating tunnel current via an empty layer. As a result, it is possible to generate tunnel current even when adopting a thicker insulating layer than that of the conventional tunnel magnetic resistance element.
Inventors:
Hidekazu Tanaka
Tomoji Kawai
Tomoji Kawai
Application Number:
JP2003579288A
Publication Date:
September 09, 2009
Filing Date:
March 25, 2003
Export Citation:
Assignee:
Japan Science and Technology Agency
International Classes:
H01L33/26; H01L43/08; G01R33/09; H01F10/193; H01F10/32; H01L21/8246; H01L27/105; H01L29/82; H01L29/868
Domestic Patent References:
| JP6097531A | ||||
| JP10150232A | ||||
| JP11354859A | ||||
| JP10186011A | ||||
| JP2001085763A | ||||
| JP2001352113A |
Attorney, Agent or Firm:
Kenzo Hara International Patent Office