Title:
メモリモジュールおよびメモリ用補助モジュール
Document Type and Number:
Japanese Patent JP4346369
Kind Code:
B2
Abstract:
It is aimed at not only enabling access to an inaccessible SDRAM area from a PC which only outputs A0 through A11 signals, but also making a common memory module connectable to earlier or latest PCs independently of their models. According to the construction, a connected PC (computer) inputs a high-order address signal A12. It is determined whether or not the input A12 signal is set to a state different from an unused state. A determination signal is generated so as to indicate a state corresponding to a determination result. When the determination signal indicates a changed state, the PC inputs A0 through A12 signals and supplies them to a memory chip 20. When the determination signal indicates an unchanged state, the PC inputs A0 through A11 signals and a select signal. The A12 signal is generated based on the input select signal. The memory chip 20 is supplied with the A12 signal and the input A0 through A11 signals.
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Inventors:
Motohiko Bungo
Tadashi Arakawa
Tadashi Arakawa
Application Number:
JP2003206790A
Publication Date:
October 21, 2009
Filing Date:
August 08, 2003
Export Citation:
Assignee:
Melco Holdings Co., Ltd.
International Classes:
G06F12/06; G06F12/00
Domestic Patent References:
| JP2004094785A | ||||
| JP9231747A |
Attorney, Agent or Firm:
Toshiyuki Yokoi