Title:
半導体パッケージ
Document Type and Number:
Japanese Patent JP4361223
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To meet the requirement for developing a technique capable of surely preventing a release or the like of a conductive layer on a metal post on a wafer, since there is a possibility of the release or the like of the layer by a stress operating at the post when the post on the wafer is connected as a terminal to a circuit board or the like, in a semiconductor package of a wafer level CSP(ChipSize/Scale Package) or the like using no circuit board (interposer). SOLUTION: The semiconductor package comprises the post 7 obtained by imparting an easily deformable directionality by coating the conductive layer 162 on a protrusion 4 made of a resin on an insulating layer of the wafer 1, and further by the deforming position or the like of a side face conductive layer 6f formed on the side face 4c of the protrusion 4. Thus, the package can efficiently absorb the stress at the connecting time to the circuit board.
Inventors:
Masatoshi Inaba
Toshiaki Inoue
Takanao Suzuki
Toshiki Sadakata
Toshiaki Inoue
Takanao Suzuki
Toshiki Sadakata
Application Number:
JP2001079537A
Publication Date:
November 11, 2009
Filing Date:
March 19, 2001
Export Citation:
Assignee:
Fujikura Ltd.
International Classes:
H01L23/12; H01L21/60
Domestic Patent References:
| JP2001332653A | ||||
| JP2000058706A | ||||
| JP2000353716A |
Foreign References:
| WO2000077844A1 |
Attorney, Agent or Firm:
Masatake Shiga
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
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