Title:
付加バンプを用いたパッケージ上の支持制御ゲート接続
Document Type and Number:
Japanese Patent JP4374427
Kind Code:
B2
Abstract:
A more robust mechanical connection is provided between a semiconductor device and the device package by adding one or more bumps to the gate connection without adding more gate pad area. A nonconductive layer covers the area around the gate pad and extends over the source area. One or more bumps fabricated on the nonconductive layer provide mechanical strength and support to the gate pad connection. The added bumps are not electrically connected to either the gate or the source. The package connections must be altered, both to fit the added bumps on the control gate, and to connect with fewer bumps on the source.
Inventors:
Bendall Earl. Evan
Application Number:
JP2003577310A
Publication Date:
December 02, 2009
Filing Date:
March 13, 2003
Export Citation:
Assignee:
Fairchild Semiconductor Corporation
International Classes:
H01L21/60; H01L23/52; H01L21/3205; H01L21/44; H01L23/48; H01L23/485; H01L23/488; H01L29/40; H01L29/772; H01L29/78; H01L
Domestic Patent References:
| JP10233509A | ||||
| JP9307103A |
Foreign References:
| WO2001004164A1 |
Attorney, Agent or Firm:
Motohiko Fujimura
Tsuneyuki Kitajima
Shigeyuki Nagaoka
Tsuneyuki Kitajima
Shigeyuki Nagaoka
Previous Patent: ベンゾ（ｂ）チエピン−１，１−ジオキサイド誘導体、その製造方法、こ...
Next Patent: 尿素置換されたおよびウレタン置換されたアシル尿素、それらの製造方法...
Next Patent: 尿素置換されたおよびウレタン置換されたアシル尿素、それらの製造方法...