Title:
トランジスタアレイ基板及びディスプレイパネル
Document Type and Number:
Japanese Patent JP4379278
Kind Code:
B2
Abstract:
A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating filminserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on thesubstrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.
Inventors:
Satoshi Shimoda
Tomoyuki Shirasaki
Jun Ogura
Tomoyuki Shirasaki
Jun Ogura
Application Number:
JP2004273532A
Publication Date:
December 09, 2009
Filing Date:
September 21, 2004
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
G09F9/30; H01L27/32; H01L51/50
Domestic Patent References:
| JP2000349298A | ||||
| JP2003133079A | ||||
| JP2003195810A | ||||
| JP2003330387A | ||||
| JP2004101948A |
Attorney, Agent or Firm:
Hiroshi Arafune
Yoshio Arafune
Yoshio Arafune