Title:
半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP4379693
Kind Code:
B2
Abstract:
A first semiconductor element (4) is mounted on a base plate (1), and is in a sealed state by the periphery thereof being covered by an insulation member (16), and the upper surface thereof being covered by an upper insulation film (17). An upper wiring layer (20, 24) formed on the upper insulation film (17), and the lower wiring layer (33, 37) formed below the base plate (1) via lower insulationfilms (31, 34) are connected by conductors (43). A second semiconductor element (40) is mounted exposed, being connected to the lower wiring layer (33, 37).
Inventors:
Shinji Wakisaka
Farewell
Farewell
Application Number:
JP2003379547A
Publication Date:
December 09, 2009
Filing Date:
November 10, 2003
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
H01L23/52; H01L25/18; H01L21/3205; H01L23/12; H01L25/10; H01L25/11
Domestic Patent References:
| JP2001274034A | ||||
| JP200144641A | ||||
| JP9321408A |