To provide a semiconductor storage device which utilizes row redundancy of a ROM macro.
The semiconductor storage device is provided with a memory cell array provided with a plurality of word lines extending in a row direction and a plurality of bit lines extending in a column direction. In the positions where the plurality of word lines and the plurality of bit lines cross with each other, memory cells each consisting of a series circuit of a switching element and a program element are arranged. Furthermore, the semiconductor storage device is provided with a redundancy memory cell array having series circuits arranged at each of positions where spare word lines and bit lines which extend in the row direction of the line and whose numbers are equal to those of inputs and outputs cross with each other, a row decoder for driving the plurality of word lines at the memory cell array, a row decoder adding circuit for driving the plurality of spare word lines, a pre-charging circuit for pre-charging the plurality of bit lines; a column selection circuit connected to the pre-charge circuit to select a bit line; and a sense amplifier circuit connected to the column selection circuit to detect data stored in a memory cell.
COPYRIGHT: (C)2005,JPO&NCIPI
Kazuya Yamaguchi
Toshiba Corporation
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Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu