Title:
相関器
Document Type and Number:
Japanese Patent JP4388943
Kind Code:
B2
Abstract:
Object: Even in the case where a receiving signal including a long delayed path having an equivalent power are received, deterioration of the receiving characteristics caused by inter symbol interference is reduced by reducing the variation of the maximum correlation time location and stabilizing the FFT time synchronization. Solution: By correlation calculation method of the correaltor 20, the receiving signal S 19 is inputted, three correlation values having different time locations from each other are calculated by the delay circuits 21 - 2 - 21 - 5, the multiplying circuits 22 - 1 - 22 - 3, and the integration circuit 23 - 1 - 23 - 3, the three correlation values thereof are added by the adding circuit 24, and the above adding result is outputted as one correlation value. Consequently, since a strong correlation appears in the midpoint between the main arriving path and the long-delayed path when the long-delayed path having the equivalent power to the main arriving path exists, jitter of the time synchronization thereof can be restrained.
Inventors:
Hirotsugu Akahori
Application Number:
JP2006287153A
Publication Date:
December 24, 2009
Filing Date:
October 23, 2006
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
International Classes:
H04J11/00
Domestic Patent References:
| JP2005102121A | ||||
| JP2005198266A | ||||
| JP2002280997A | ||||
| JP2004304591A | ||||
| JP2005151396A | ||||
| JP2000165338A |
Attorney, Agent or Firm:
Kakimoto Yasunari