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Title:
ホール素子パッケージ及び複合実装モジュール
Document Type and Number:
Japanese Patent JP4400881
Kind Code:
B2
Abstract:

To further reduce the size of the entire packaging module by mounting a semiconductor chip such as a Hall element sideways, in a semiconductor package and a composite packaging module using the same.

The semiconductor package comprises a substrate 11 formed of an insulating material, the Hall element 6 mounted on the side face of the substrate 11, and a resin seal 12 which resin-seals the Hall element 6 on the side face of the substrate 11. The substrate 11 includes a first electrode pattern 13 which is formed on the side face of the substrate 11 and is electrically connected to the Hall element 6, and a second electrode pattern 14 for wire bonding which is connected to the first electrode pattern 13 and is formed on the top face of the substrate. Accordingly, a wire W1 can be directly connected to the second electrode pattern 14, can eliminate the necessity of forming an electrode pattern and a space for wire bonding on the circuit board 15, and can further reduce the size of the entire packaging module.

COPYRIGHT: (C)2006,JPO&NCIPI


Inventors:
Shin Shimozawa
Application Number:
JP2004349861A
Publication Date:
January 20, 2010
Filing Date:
December 02, 2004
Export Citation:
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Assignee:
Citizen Electronics Co., Ltd.
Asahi Kasei Electronics Co., Ltd.
International Classes:
H01L25/16; G01R33/07; H01L43/04
Domestic Patent References:
JP2001156244A
JP9213833A
JP2004069695A
JP2004265997A
JP2002050714A
JP2006054319A
Attorney, Agent or Firm:
Hideyuki Sugiura