Title:
DRAM積層パッケージ並びにDRAM積層パッケージの試験および救済方法
Document Type and Number:
Japanese Patent JP4401319
Kind Code:
B2
Abstract:
The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.
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Inventors:
Yuji Soda
Shuji Kikuchi
Katsunori Hirano
Ichiro Anjo
Mitsuaki Katagiri
Shuji Kikuchi
Katsunori Hirano
Ichiro Anjo
Mitsuaki Katagiri
Application Number:
JP2005110752A
Publication Date:
January 20, 2010
Filing Date:
April 07, 2005
Export Citation:
Assignee:
株式会社日立製作所
エルピーダメモリ株式会社
エルピーダメモリ株式会社
International Classes:
G11C29/12; G01R31/28; G11C11/401; G11C29/44; G11C29/56
Domestic Patent References:
| JP2003223799A | ||||
| JP9504654A | ||||
| JP2003036694A |
Foreign References:
| WO2001056038A1 |
Attorney, Agent or Firm:
Polaire Patent Business Corporation
Katsuo Ogawa
Kyosuke Tanaka
Katsuo Ogawa
Kyosuke Tanaka