Title:
半導体装置及びその検査方法
Document Type and Number:
Japanese Patent JP4407785
Kind Code:
B2
Abstract:
An IC (semiconductor device) comprises a package substrate provided on its face side with a plurality of wiring patterns such as electrode lands and wirings and provided on its back side with a plurality of electrode bumps corresponding to the wiring patterns, an IC chip mounted on the face side of the package substrate in a face-up manner, a sealing resin sealing the IC chip, and an indication provided on the back side of the package substrate for indicating the position of the IC chip. A method of inspecting a failure reason in the case of some failure of the IC chip comprises the steps of forming an opening by removing from the back side the package substrate in the region surrounded by the indication, mounting the IC chip on a test substrate, passing an electric current to the IC chip for operation, and inspecting and analyzing the reason of failure by a photo-emission analyzing method. The photo-emission analysis can be conducted without processing an upper layer wiring portion or the like of the IC chip.
Inventors:
Yuichiro Ikenaga
Yasushi Otsuka
Yasushi Otsuka
Application Number:
JP2000324153A
Publication Date:
February 03, 2010
Filing Date:
October 24, 2000
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G01R1/06; H01L23/12; G01R31/302; H01L23/544; G01R31/28; G01R31/311
Domestic Patent References:
| JP9199540A | ||||
| JP5335438A |
Attorney, Agent or Firm:
Osamu Matsumura