半導体装置の製造方法 - Renesas Technology Corp.

Title:

半導体装置の製造方法

Document Type and Number:

Japanese Patent JP4409455

Kind Code:

B2

Abstract:

A connection method is disclosed for a high-performance semiconductor system. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs. Semiconductor chips and the interposer chips are polished by grinding at their rear surfaces, holes are formed at rear surface positions corresponding to external electrode parts on the device side (front surface side) so that the holes extend to front surface electrodes, and metal plating films are applied to the side walls of the holes and rear surface side. Metal bumps of another semiconductor chip laminated at an upper stage being press-fitted into the holes applied with the metal plating films through deformation and being geometrically calked in the through holes formed in the semiconductor chip so as to electrically connected thereto.

Inventors:

Naoki Tanaka
Tamotsu Yoshimura
Takahiro Naito
Takashi Akazawa

Application Number:

JP2005022478A

Publication Date:

February 03, 2010

Filing Date:

January 31, 2005

Export Citation:

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