Title:
半導体メモリ用遅延固定ループ装置
Document Type and Number:
Japanese Patent JP4411504
Kind Code:
B2
Abstract:
Disclosed is a delay locked loop (DLL) for use in a semiconductor memory device, which has the ability to reduce or eliminate a power supply noise, a random noise or other irregular noise. The DLL includes a controllable delay modification unit for delaying a clock signal fed thereto to produce a time-delayed signal, a comparator for comparing the time-delayed signal from the modification block and a reference signal, and determining an addition or subtraction of the time delay according to the compared result to produce a corresponding output signal, and a delay control unit for counting the number that the corresponding output signal is activated, and producing a signal for controlling the addition or the subtraction of the time delay to the modification unit, if the counted value satisfies a predetermined condition.
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Inventors:
Korea Jong
Application Number:
JP2001000035A
Publication Date:
February 10, 2010
Filing Date:
January 04, 2001
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/413; H03K5/135; G11C7/22; G11C8/00; G11C11/407; G11C11/4076; H03L7/081; H03L7/089; H03L7/093
Domestic Patent References:
| JP11186903A | ||||
| JP10117142A | ||||
| JP11261408A | ||||
| JP10313304A | ||||
| JP1165699A | ||||
| JP10112182A |
Attorney, Agent or Firm:
Patent Business Corporation Saegusa International Patent Office