Title:
スルーレート制限回路および光ディスク装置
Document Type and Number:
Japanese Patent JP4425786
Kind Code:
B2
Abstract:
In a slew rate limiter, a slew rate is limited so as not to pass a signal varying more abruptly than a wobble signal included in a difference signal generated by a differential amplifier, and this limited slew rate is used to process the difference signal to be outputted. That is, the slew rate limiter removes a signal varying more abruptly than a wobble signal included in a difference signal DIFO, and then outputs only the wobble signal. A DAC generates an offset voltage. An adder is used to add this offset voltage to the wobble signal from the slew rate limiter. The signal obtained by this addition as a slice level is compared by a comparator with the difference signal, thereby reproducing an LPP signal.
Inventors:
Makoto Kobayashi
Tomioka Koji
Kazunari Sasaki
Tomioka Koji
Kazunari Sasaki
Application Number:
JP2004506178A
Publication Date:
March 03, 2010
Filing Date:
May 16, 2003
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H03G11/00; G11B7/005; G11B7/13; G11B20/10; G11B20/20; G11B7/007
Domestic Patent References:
| JP3160673A | ||||
| JP7162277A | ||||
| JP7014197A | ||||
| JP2001312823A | ||||
| JP2000182257A | ||||
| JP2000163760A | ||||
| JP2000268371A | ||||
| JP5052879A | ||||
| JP9128908A | ||||
| JP8287478A | ||||
| JP2000068802A | ||||
| JP2000221254A | ||||
| JP2002074682A | ||||
| JP2000231726A |
Attorney, Agent or Firm:
Tetsuya Mori
Yoshiaki Naito
Cui Shu Tetsu
Yoshiaki Naito
Cui Shu Tetsu