Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4428504
Kind Code:
B2
Abstract:
The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.
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Inventors:
Akihiro Hayashi
Takeshi Negishi
Hiroshi Toyoshima
Takeshi Negishi
Hiroshi Toyoshima
Application Number:
JP2003118528A
Publication Date:
March 10, 2010
Filing Date:
April 23, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F3/00; H01L21/822; G11C7/00; H01L21/82; H01L27/04; H03K19/00; H03K19/003; H03K19/0175; H04L25/02; H03K17/16
Domestic Patent References:
| JP2002135102A | ||||
| JP2000223585A | ||||
| JP1093145A |
Foreign References:
| WO2002031979A1 |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka